DMA_ENA=DISABLE, DBLBUF_ENA=DISABLE, CNT_ENA=DISABLE, INT_DMA_REQ=CLEAR_ON_ANY_WRITE_T
DAC Control register. This register controls DMA and timer operation.
| INT_DMA_REQ | DMA interrupt request 0 (CLEAR_ON_ANY_WRITE_T): Clear on any write to the DACR register. 1 (SET_BY_HARDWARE_WHEN): Set by hardware when the timer times out. |
| DBLBUF_ENA | Double buffering 0 (DISABLE): Disable 1 (ENABLE_WHEN_THIS_BI): Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter. |
| CNT_ENA | Time-out counter operation 0 (DISABLE): Disable 1 (ENABLE): Enable |
| DMA_ENA | DMA access 0 (DISABLE): Disable 1 (ENABLE_DMA_BURST_RE): Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672). |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |